1. Field of the Invention
The present invention relates to a transistor output circuit, and in particular, the present invention relates to a transistor output circuit featuring a reduced power consumption and a high speed operation.
2. Description of the Related Art
Recently, a digital communication technology is widely used in a portable communication equipment and so on, and in addition, a trend for an increased communication capacity and higher speed of communication is in progress. In these portable and high speed digital communication technologies, it becomes more popular that the equipment is provided in a more compact size, light-weighted, and a battery operated form.
As one of IC circuits capable of realizing a high speed digital communication, there is an ECL (Emitter-Coupled-Logic) circuit comprised of bipolar transistors.
In the bipolar IC (Integrated Circuit) circuit comprising bipolar transistors, an analog signal after being subjected to a signal processing is converted in an AID (Analog to Digital) converter to a digital signal and is derived from its output terminal, and this output signal is supplied through the above-mentioned ECL circuit to a CMOS (Complementary Metal Oxide Semiconductor) digital circuit for a digital signal processing.
As shown in FIG. 3, in the conventional ECL circuit for use in a high speed signal processing, pulse signals of opposite phase are supplied to respective bases of a bipolar transistors Q1 and Q2 which have their emitters connected at a common connection point, and this common connection point is further connected to a reference potential VEE (xe2x88x925.2 V, for example) via a constant current supply I0. On the other hand, a collector of the transistor Q1 is connected to a reference potential of 0V, for example; and a collector of the transistor Q2 is connected via a load resistance R1 to the reference potential of 0V.
Further, it is arranged in the circuit of FIG. 3 such that a base of an output transistor Q3 is connected with a common connection point between the collector of the transistor Q2 and the load resistance R1, a collector of the transistor Q3 is connected to the reference potential of 0V, and an emitter of the transistor Q3 is set normally open, and then an output signal is taken out from an output terminal OUT.
Further, the emitter of the transistor Q3 is connected to the reference potential VEE (xe2x88x925.2V) via a resistance R2 for setting its current from the output terminal OUT. In an output through-rate at a rising time of this ECL circuit is determined by a faculty of its transistor, and a falling time is determined by a value of the resistance R2 connected to the emitter of the transistor Q3, namely the output terminal OUT. In order to speed up its falling time, the resistance value of the resistance R2 has to be small, but this causes an increased dissipation of current.
Now, with reference to FIG. 4, an example of a so-called active pull down circuit or a CCPP (Complementary Coupled Push Pull) circuit will be described.
In differentially connected NPN type transistors Q11 and Q12, a pair of opposite phase signal s are supplied to bases of these transistors Q11 and Q12 , and respective emitter thereof are connected together at a common connection point connected to a reference potential GND of 0V via a constant current supply I10. Further, a collector of the NPN transistor Q11 is connected to a reference power supply Vcc via a load resistance R11, and a collector of the NPN transistor Q12 is also connected to the reference power supply Vcc via a load resistance R12.
A common connection point between the collector of the NPN transistor Q11 and the load resistance R11 is connected via an inverting amplifier A1 to a base of an emitter follower NPN transistor Q14 which constitutes a voltage level shift circuit in the next stage. A collector of the transistor Q14 is connected to the reference power supply Vcc, and its emitter is connected to the reference potential GND of 0V via a constant current source 112.
Further, a common connection point between the collector of the NPN transistor Q12 and the load resistance R12 is connected to a base of an emitter follower PNP transistor Q13 which constitutes a voltage level shift circuit in the next stage. A collector of the transistor Q13 is connected to the reference potential GND of 0V, and an emitter thereof is connected to the reference power supply Vcc of 5V via a constant current supply I11.
An output stage of the circuit in FIG. 4 is comprised of a complementary PNP transistor and NPN transistor, wherein the emitter of the PNP transistor Q13 is connected to a base of an NPN transistor Q15, and a collector of this NPN transistor Q15 is connected to the reference potential GND of 0V.
The emitter of the transistor Q14 is connected to a base of the PNP transistor Q16, and an emitter of the PNP transistor Q16 is connected to an emitter of the NPN transistor Q15. A collector of the PNP transistor Q16 is connected to the reference potential GND of 0V.
Respective emitters of these PNP transistor Q16 and NPN transistor Q15 are connected together at a common connection point which is connected to an output terminal OUT, and an output signal is derived from the output terminal OUT.
Differential signals having an opposite phase to each other are supplied to respective bases of the NPN transistors Q11 and Q12, which constitute a differential amplifier, in which after respective signals supplied to these bases are inverted (180xc2x0 phase shift), they are derived from respective collectors thereof. A gain of this differential amplifier is determined by one half of its emitter resistance and a ratio of the load resistances R11 to R12.
Signals that are amplified in the differential amplifier up to a predetermined amplitude (pulse waveforms in most cases) are supplied to the bases of the NPN transistor Q14 and the PNP transistor Q13, respectively, which constitute an emitter follower circuit in the next stage, and in which Vf voltage (forward voltage across the base and emitter of transistor; approximately 0.7V) is shifted. More particularly, its signal output to the collector of the NPN transistor Q11 is inverted in the inverting amplifier, then caused to drop by Vf (V) in the NPN transistor Q14, and is supplied to the base of the PNP type output transistor Q16.
On the other hand, the signal output to the collector of the NPN transistor Q12 is caused to rise by Vf (V) in the PNP transistor Q13, then is supplied to the base of the NPN type output transistor Q15.
Now, assuming that the base of the NPN transistor Q11 is at xe2x80x9cHxe2x80x9d level, and the base of the NPN transistor Q12 is at xe2x80x9cLxe2x80x9d level, then after inversion of these signals therein, there are derived a signal of xe2x80x9cLxe2x80x9d level at the collector of the transistor Q11, and a signal of xe2x80x9cHxe2x80x9d level at the collector of the transistor Q12.
Thus, the base of the PNP transistor Q13 becomes xe2x80x9cHxe2x80x9d (=Vcc) level, and also the emitter thereof becomes xe2x80x9cHxe2x80x9d (=Vcc) level, as a result, because the base of the NPN type output transistor Q15 also becomes xe2x80x9cHxe2x80x9d (=Vccxe2x88x92Vf) level, it turns ON so as to flow a current from the reference power supply Vcc of 5V toward an output side across the collector and the emitter of the transistor Q15. Therefore, the output terminal OUT becomes xe2x80x9cHxe2x80x9d (=Vccxe2x88x92Vf) level.
On the other hand, the base of the NPN transistor Q14 in the next stage is supplied with a signal of xe2x80x9cHxe2x80x9d (Vcc) level as inverted in the inverting amplifier A1. This inverted (pulse) signal of xe2x80x9cHxe2x80x9d level when transferred to the next stage causes the emitter of the next stage NPN transistor Q14 to become xe2x80x9cHxe2x80x9d (Vccxe2x88x92Vf) level. As a result, because the base of the output PNP transistor Q16 also becomes xe2x80x9cHxe2x80x9d (Vccxe2x88x92Vf) level, the transistor Q16 turns OFF, and the emitter terminal thereof becomes open. Thereby, the output terminal OUT becomes an xe2x80x9cHxe2x80x9d level potential that is determined by the emitter of the NPN transistor Q15.
Alternatively, assuming that the base of the NPN transistor Q11 is xe2x80x9cLxe2x80x9d level, and the base of the NPN transistor Q12 is xe2x80x9cHxe2x80x9d level, these signals are inverted therein so that an xe2x80x9cHxe2x80x9d level signal is derived at the collector of the transistor Q11, and a xe2x80x9cLxe2x80x9d level signal is derived at the collector of the transistor Q12.
As a consequence, the base of the PNP transistor Q13 becomes xe2x80x9cLxe2x80x9d (=Vccxe2x88x92VL1) level, and the emitter thereof becomes xe2x80x9cLxe2x80x9d (=Vccxe2x88x92VL +Vf) level. As a result, the base of the output NPN transistor Q15 also becomes xe2x80x9cLxe2x80x9d (=Vccxe2x88x92VL+Vf) level.
On the other hand, the xe2x80x9cHxe2x80x9d level signal at the collector of the NPN transistor Q11 is inverted by the inverting amplifier A1 in the next stage to become xe2x80x9cLxe2x80x9d level. This xe2x80x9cLxe2x80x9d level signal (in pulses) is transferred to the base of the NPN transistor Q14 thereby setting the same at xe2x80x9cLxe2x80x9d (=Vccxe2x88x92VL2) level, further setting the emitter thereof at xe2x80x9cLxe2x80x9d (=Vccxe2x88x92VL2 xe2x88x92Vf) level, thus, as a consequence, the base of the output PNP transistor Q16 also becomes xe2x80x9cLxe2x80x9d (=Vccxe2x88x92VL2xe2x88x92Vf) level. Therefore, the output PNP transistor Q16 turns ON, thereby causing a current to flow from the load capacitance C and the resistance connected with the output terminal OUT to the reference potential GND of 0V via the emitter and collector of the PNP transistor Q16.
As a result, its emitter potential drops. If its output level (Vccxe2x88x92VL1) and the output level (Vccxe2x88x92VL2) of the inverting amplifier A1 are set such that VL1 greater than  greater than VL2, the transistor Q15 becomes off, allowing only the transistor Q16 to be on.
Further, there is a TTL circuit in addition to the ECL circuit for this purpose. An example of a high speed TTL (Transistor-Transistor-Logic) output circuits using the same is shown in FIG. 5. NPN transistors Q21 and Q22, in which opposite phase signals are supplied to their bases respectively by way of an input terminal IN, have their respective emitters connected; together at a common connection point, and this common connection point is connected to a reference potential GND of 0V via a constant current source 120.
On the other hand, a resistance R21 that is connected to a collector of the NPN transistor Q21 is connected to a reference potential Vcc of 5V. Further, a collector of the NPN transistor Q22 is connected to the reference potential Vcc of 5V via a resistance R22.
The collector of the NPN transistor Q21 is connected to a base of an NPN transistor Q23, a collector of the transistor Q23 is connected to the reference potential Vcc of 5V, and an emitter thereof is connected to the reference potential of 0V via a constant current source I21.
The collector of the NPN transistor Q22 is connected to a base of an NPN transistor Q24 in the next stage, a collector of the transistor Q24 is connected to the reference potential Vcc of 5V, and an emitter thereof is connected to the reference potential GND of 0V via resistances R23 and R24.
A collector of an NPN transistor Q25 is connected to the reference potential Vcc of 5V, and an emitter thereof is connected to an output terminal OUT and also to a collector of an NPN transistor Q26. The base of the NPN transistor Q24 is connected to the output terminal OUT via diodes D21 and D22. Further, a base of the NPN transistor Q26 is connected with a common connection point between the resistance R23 and the resistance R24. An emitter of this NPN transistor Q26 is connected to the reference potential GND of 0V.
Now, if a signal of xe2x80x9cHxe2x80x9d level is supplied to the base of the transistor Q21, and a signal of xe2x80x9cLxe2x80x9d level is supplied to the base of the transistor Q22, a signal of xe2x80x9cLxe2x80x9d level is derived at the collector of the NPN transistor Q21 due to inversion of its input signal. Further, at the collector of the NPN transistor Q22, a signal of xe2x80x9cHxe2x80x9d level is derived.
The signal of xe2x80x9cLxe2x80x9d level derived at the collector of the NPN transistor Q21 is supplied to the base of the NPN transistor Q23, then a signal of xe2x80x9cLxe2x80x9d level is derived from the emitter of the NPN transistor Q23. Then, this xe2x80x9cLxe2x80x9d level signal is supplied to the base of the NPN transistor Q25 in an output stage, as a consequence, setting this transistor Q25 in off state.
On the other hand, the collector of the NPN transistor Q22 becomes xe2x80x9cHxe2x80x9d level, and this xe2x80x9c14xe2x80x9d level signal is applied to the base of the NPN transistor Q24 and to the anode of the diode D21 in the following stage. This xe2x80x9cHxe2x80x9d level signal is divided by the resistances R23 and R24, and the common connection point between the resistances R23 and R24 becomes xe2x80x9cHxe2x80x9d level, as a result, a xe2x80x9cHxe2x80x9d level signal is supplied to the base of the output NPN transistor Q26. Thus, the NPN transistor Q26 turns on causing the collector output to drop to xe2x80x9cLxe2x80x9d level. This output NPN transistor Q26 tends to drop down to Vcesat.
Thereby, a current is caused to flow from the load resistance and the capacitance which are connected to the output terminal OUT via the collector and the emitter of the NPN transistor Q26 to the reference potential GND of 0V, thereby causing the output terminal OUT to become xe2x80x9cLxe2x80x9d level.
At this time, when the level of this output terminal OUT drops excessively, the diodes D21 and D22 become conductive so that, if a ratio of R23 and R24 is R23 : R24=1:2, the emitter and the base of the transistor Q24 become 1.5Vf and 2.5Vf respectively, thereby clamping the collector at 0.5 Vf. Therefore, xe2x80x9cLxe2x80x9d level of the output level becomes 0.5Vf.
In the next, when the xe2x80x9cLxe2x80x9d level signal is applied to the base of the differential transistor Q21 while the xe2x80x9cHxe2x80x9d level signal is applied to the base of the transistor Q22, respectively, the xe2x80x9cHxe2x80x9d level signal is derived at the collector of the NPN transistor Q21 due to inversion of its input signal. Further, at the collector of the NPN transistor Q22, the xe2x80x9cLxe2x80x9d level signal is derived.
The xe2x80x9cHxe2x80x9d level signal derived from the collector of the NPN transistor Q21 is supplied to the base of the NPN transistor Q23, and the xe2x80x9cHxe2x80x9d level signal is derived from the emitter thereof. Then, this xe2x80x9cHxe2x80x9d level signal is supplied to the base of the NPN transistor Q25 in the output stage, thereby consequently causing this transistor Q25 to turn on. Therefore, the output xe2x80x9cHxe2x80x9d level becomes Vccxe2x88x922Vf.
On the other hand, the xe2x80x9cLxe2x80x9d level signal derived from the collector of the NPN transistor Q22 is applied to the base of the NPN transistor Q24 and to the anode of the diode D21 in the next stage. Further, this xe2x80x9cLxe2x80x9d level signal is divided by the resistances R23 and R24, and a common connection point there-between becomes xe2x80x9cLxe2x80x9d level. As a result, the xe2x80x9cLxe2x80x9d level signal is supplied to the base of the output NPN transistor Q26. Thereby, the NPN transistor Q26 turns off, causing the output collector to become open.
Therefore, because the NPN transistor Q25 being in an operating state, a current flows from the reference potential Vcc of 5V to the output terminal OUT via the collector and the emitter thereof. Thereby, the potential of the output terminal OUT rises to become xe2x80x9cHxe2x80x9d level.
As described above, the ECL circuit shown in FIG. 3 is of the open emitter, and the emitter output current is set up from this emitter using an external resistance. In order to achieve a high speed operation and appropriate impedance matching, this set-up current is approximately several mA. In case the number of ECL circuits within IC increases, a total current increases, thereby increasing a current dissipation. Therefore, there is a problem that it is not suitable for use in the portable communication equipment, which is driven by batteries.
Further, as for the active pull-down circuit (CCPP) shown in FIG. 4, because it uses PNP transistors, and ft of these transistors is lower than that of NPN transistors, there is a problem that operation speed of the circuit becomes low.
Still further, in the case using the TTL circuit shown in FIG. 5, the operational speed of the circuit can be improved because of using NPN transistors. However, there is a problem that because its output stage transistor repeats saturation operation, its operation speed is not always high enough, and that its circuit tends to be affected by fluctuations in the power supply voltage and the temperature.
As described above, the conventional transistor output circuits have such problems that the transistor output circuit using ECL circuits consumes a large power, the transistor output circuit using the active pull-down circuits (CCPP) is not adequate in its operational speed, and the transistor output circuit using TTL circuits is also not high enough in operational speed and is unstable relative to fluctuations in the supply voltage and the temperatures.
The object of the present invention is to solve the above-mentioned problems associated with the conventional transistor output circuits by utilizing a relatively simple method and to provide for a novel transistor output circuit featuring a reduced power consumption, high processing speed, and stable operation, economically at a reduced cost.
In order to accomplish the above-mentioned object of the invention, a transistor output circuit according to one aspect of the invention is provided, comprising: a first and a second transistors, respective bases of which transistors are supplied with an opposite phase signal, respective emitters thereof are connected at a common connection point, and respective collectors thereof are connected to a first reference potential via each resistance; a third transistor, the base of which is connected to the collector of the first transistor, and the collector of which is connected to the first reference potential; a level shift, one end of which is connected to the emitter of the third transistor; a fourth transistor the base of which is connected to the collector of the second transistor and to another end of the first level shift, and the collector of which is connected to the first reference potential; a second level shift one end of which is connected to the emitter of the fourth transistor; a constant current supply, connected between another end of the second level shift and a second reference potential, and provided with a bias for setting a current at discretion; and a fifth transistor the base of which is connected to a common connection point between the constant current supply and the other end of the second level shift, and the collector of which is connected to the emitter of the third transistor, wherein: an output is obtained across the second potential and a common connection point between the collector of: the fifth transistor and the emitter of the third transistor.
According to another aspect of the invention, a transistor output circuit is provided, comprising: a first and a second transistors, respective bases of which transistors are supplied with an opposite phase signal, respective emitters thereof are connected at a common connection point, and respective collectors thereof are connected to a first reference potential via each resistance; a third transistor, the base of which is connected to the collector of the first transistor, and the collector of which is connected to the first reference potential; a level shift, one end of which is connected to the emitter of the third transistor; a fourth transistor the base of which is connected to the collector of the second transistor and to the other end of the first level shift, and the collector of which is connected to the first reference potential; a second level shift one end of which is connected to the emitter of the fourth transistor; a constant current supply, connected between the other end of the second level shift and a second reference potential, and provided with a bias for setting a current at discretion; a fifth transistor the base of which is connected to a common connection point between the constant current supply and the other end of the second level shift, and the collector of which is connected to the emitter of the third transistor; and a voltage supply for supplying a predetermined voltage to the common connection point between the constant current supply and the other end of the second level shift, wherein: an output is obtained across the second potential and a common connection point between the collector of the fifth transistor and the emitter of the third transistor.
According to still further aspect of the invention, a transistor output circuit is provided, comprising: a first and a second transistors, respective bases of which transistors are supplied with an opposite phase signal, respective emitters thereof are connected at a common connection point, and respective collectors thereof are connected to a first reference potential via each resistance; a third transistor, the base of which is connected to the collector of the first transistor, and the collector of which is connected to the first reference potential; a level shift, one end of which is connected to the emitter of the third transistor; a fourth transistor the base of which is connected to the collector of the second transistor and to the other end of the first level shift, and the collector of which is connected to the first reference potential; a second level shift one end of which is connected to the emitter of the fourth transistor; a first constant current supply, connected between the other end of the second level shift and a second reference potential, and provided with a bias for setting a current at discretion; a fifth transistor the base of which is connected to a common connection point between the first constant current supply and the other end of the second level shift, and the collector of which is connected to the emitter of the third transistor; a sixth and a seventh transistors corresponding to the above-mentioned fourth and the fifth transistors; a third and a fourth level shifts corresponding to the above-mentioned first and second level shifts; a dummy output stage circuit comprising a second constant current supply corresponding to the above-mentioned first constant current supply; and an inverting amplifier circuit for inverting and amplifying an output of the dummy output stage circuit, wherein: an output of the inverting amplifier circuit is fed back to, the first and the second constant current supplies as a bias voltage, and an output is obtained across the second reference potential and a common connection point between the collector of the fifth transistor and the emitter of the third transistor.
By provision of the above-mentioned arrangements according to the invention, a novel transistor output circuit can be realized economically at a reduced cost, which features a relatively simple circuitry configuration, reduced power consumption, high operational speed, and an improved stability of operation.